Network devices, such as routers or switches, often include memory devices for buffering packets ready for transmission, for example to implement traffic management of different flows transmitted by the network devices, or merely to temporarily store packets when transmit ports are not immediately available for transmission. Memory controllers coupled to such memory devices typically include queues for queuing write requests for writing packets to the memory devices and read request queues for queuing read requests for reading packets from the memory devices. The memory controller implements a suitable scheduling scheme for providing access to the memory device such that write requests and read requests can be executed in some fair and/or efficient manner. Generally, writing packets to the memory device and reading packets from the memory device creates a load on a bus that connects the memory controller to the memory device.